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product structure: silicon monolithic integrated circuit this product is not designed prot ection against radioactive rays 1/28 tsz02201-0r1r0g100140-1-2 31.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 14? 001 datashee t www.rohm.com serial eeprom series automotive eeprom 105 operation i 2 c bus eeprom (2-wire) br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) general description br24axxx-wm is a serial eeprom of i 2 c bus interface method. features ? completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock (scl) and serial data (sda) ? wide temperature range -40 to +105 ? other devices than eeprom can be connected to the same port, saving microcontroller port ? 2.5v to 5.5v single power source operation most suitable for battery use ? page write mode useful for initial value write at factory shipment ? auto erase and auto end function at data rewrite ? low current consumption ? at write operation (5v) : 1.2ma (typ.) *1 ? at read operation (5v) : 0.2ma (typ.) ? at standby condition (5v) : 0.1 a (typ.) ? write mistake prevention function ? write (write protect) function added ? write mistake prevention function at low voltage ? data rewrite up to 1,000,000 times(ta Q25 ? data kept for 40 years(ta Q25 ? noise filter built in scl / sda terminal ? shipment data all address ffh packages w(typ.) x d(typ.) x h(max.) *1 br24a32-wm, br24a64-wm : 1.5ma page write number of pages 8byte 16byte 32byte product number br24a01a-wm br24a02-wm br24a04-wm br24a08-wm br24a16-wm br24a32-wm br24a64-wm br24axxx-wm capacity bit format type power source voltage sop8 sop-j8 msop8 1kbit 1288 br24a01a-wm 2.5v to 5.5v 2kbit 2568 br24a02-wm 2.5v to 5.5v 4kbit 5128 br24a04-wm 2.5v to 5.5v 8kbit 1k8 br24a08-wm 2.5v to 5.5v 16kbit 2k8 br24a16-wm 2.5v to 5.5v 32kbit 4k8 br24a32-wm 2.5v to 5.5v 64kbit 8k8 br24a64-wm 2.5v to 5.5v sop8 5.00mm x 6.20mm x 1.71mm sop- j8 4.90mm x 6.00mm x 1.65mm msop8 2.90mm x 4.00mm x 0.90mm
datasheet datasheet 2/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) absolute maximum ratings (ta=25 ) parameter symbol ratings unit remarks supply voltage v cc -0.3 to +6.5 v 450 (sop8) when using at ta=25 or higher 4.5mw to be reduced per 1 . 450 (sop-j8) when using at ta=25 or higher 4.5mw to be reduced per 1 . power dissipation pd 310 (msop8) mw when using at ta=25 or higher 3.1mw to be reduced per 1 . storage temperature tstg -65 to +125 operating temperatur e topr -40 to +105 terminal voltage \ -0.3 to v cc +1.0 v memory cell characteristics (v cc =2.5v to 5.5v) limits parameter min. typ. max unit conditions 1,000,000 - - ta Q25 number of data rewrite times *1 100,000 - - times ta Q105 40 - - ta Q25 data hold years *1 10 - - years ta Q105 shipment data all address ffh *1not 100% tested recommended operating ratings parameter symbol ratings unit power source voltage v cc 2.5 to 5.5 input voltage v in 0 to v cc v electrical characteristics (u nless otherwise specified, ta=-40 to +105 , v cc =2.5v to 5.5v) limits parameter symbol min. typ. max. unit conditions ?high? input voltage v ih 0.7 v cc - - v ?low? input voltage v il - - 0.3 v cc v ?low? output voltage 1 v ol - - 0.4 v i ol =3.0ma (sda) input leak current i li -1 - 1 a v in =0v to v cc output leak current i lo -1 - 1 a v out =0v to v cc , (sda) 2.0 *1 i cc1 - - 3.0 *2 ma v cc =5.5v,f scl =400khz, t wr =5ms, byte write, page write current consumption i cc2 - - 0.5 ma v cc =5.5v,f scl =400khz random read, current read, sequential read standby current i sb - - 2.0 a v cc =5.5v, sda ?scl= v cc a0, a1, a2=gnd, wp=gnd *1 br24a01a/02/04/08/16-wm, *2 br24a32/64-wm
datasheet datasheet 3/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) operating timing characteristics (unless otherwise specified, ta= - 40 to +105 , v cc =2.5v to 5.5v) fast-mode 2.5v Qv cc Q 5.5v standard-mode 2.5v Qv cc Q 5.5v parameter symbol min. typ. max. min. typ. max. unit scl frequency f scl - - 400 - - 100 khz data clock ?high? time t high 0.6 - - 4.0 - - s data clock ?low? time t low 1.2 - - 4.7 - - s sda, scl rise time *1 t r - - 0.3 - - 1.0 s sda, scl fall time *1 tf - - 0.3 - - 0.3 s start condition hold time t hd:sta 0.6 - - 4.0 - - s start condition setup time t su:sta 0.6 - - 4.7 - - s input data hold time t hd:dat 0 - - 0 - - ns input data setup time t su:dat 100 - - 250 - - ns output data delay time t pd 0.1 - 0.9 0.2 - 3.5 s output data hold time t dh 0.1 - - 0.2 - - s stop condition setup time t su:sto 0.6 - - 4.7 - - s bus release time before transfer start tb uf 1.2 - - 4.7 - - s internal write cycle time t wr - - 5 - - 5 ms noise removal valid period (sda, scl terminal) ti - - 0.1 - - 0.1 s wp hold time t hd:wp 0 - - 0 - - ns wp setup time t su:wp 0.1 - - 0.1 - - s wp valid time t high:wp 1.0 - - 1.0 - - s *1 not 100% tested fast-mode and standard-mode fast-mode and standard-mode are of same operations, and m ode is changed. they are di stinguished by operating speeds. 100khz operation is called standard-mode, and 40 0khz operation is called fa st-mode. this operating frequency is the maximum operating frequency, so 100khz clock may be used in fast-mode. at v cc =2.5v to 5.5v, 400khz, namely, operation is made in fastmode. (o peration is made also in standard-mode.) sync data input / output timing input read at the rise edge of scl data output in sync with the fall of scl figure 1-(a) sync data input / output timing figure 1-(b) start-stop bit timing figure 1-(c) write cycle timing figure 1-(d) wp timing at write execution at write execution, in the area from the d0 taken clock rise of the first data(1), to twr, set wp=?low?. by setting wp ?high? in the area, write can be cancelled. when it is set wp=?high? during twr, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. figure 1-(e) wp timing at write cancel sda tsu:sta tsu:sto thd:sta start bit stop bit scl thigh:wp wp sda d1 d0 ack ack data(1) data(n) twr scl sda write data ( n-th address ) stop condition start condition scl wr ack d0 sd a () sda () thd:sta thd:dat tsu:dat tbuf tpd tdh tlow thigh tr tf scl (input) (output) scl sda wp hd wp ???? wr d1 d0 a ck a ck data(1) data(n) tsu wp stop condition
datasheet datasheet 4/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) block diagram pin configuration pin descriptions function terminal name input / output br24a01a-wm br24a02-wm br24a04-wm br24a08- wm br24a16-wm br24a32-wm br24a64-wm a0 input slave address setting not connected slave address setting a1 input slave address setting not connected slave address setting a2 input slave address setting not used slave address setting gnd - reference voltage of all input / output, 0v sda input / output slave and word address, serial data input serial data output scl input serial clock input wp input write protect terminal vcc - connect the power source. 1kbit to 64kbit eeprom array control circuit high voltage generating circuit power source voltage detection 7bit 8bit 9bit 10bi t 11bit 12bit 13b it address decoder slave - word address register data register 8bit 7bit 8bit 9bit 10bi t 11bit 12bit 13b it start stop ack *1 *1 1 2 3 4 8 7 6 5 sda scl wp vcc a1 a0 a2 gnd *2 *2 *2 *1 7bit : br24a01a-wm 8bit : br24a02-wm 9bit : br24a04-wm 10bit : br24a08-wm 11bit : br24a16-wm 12bit : br24a32-wm 13bit : br24a64-wm * 2 a0=n.c. : br24a04-wm a0, a1=n.c. : br24a08-wm a0, a1= n.c. a2=don?t use : br24a16-wm 2 1 3 4 br24a01a-wm br24a02-wm br24a04-wm br24a08-wm br24a16-wm br24a32-wm br24a64-wm a0 a1 a2 gnd vcc wp scl sda 8 7 6 5 (top view)
datasheet datasheet 5/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) figure 4. l output voltage vol1-iol1 (v cc =2.5v) figure 5. input leak current ili (scl,wp) figure 2. h input voltage vih1,2 (scl,sda,wp) figure 3. l input voltagevil1,2 (scl,sda,wp) typical performance curves (the following values are typ. ones.) 0 1 2 3 4 5 6 0 1 2 3 4 5 6 vih[v] ta=105 ta=-40 ta=25 spec vcc[v] 0 1 2 3 4 5 6 0 1 2 3 4 5 6 vil[v] ta=105 ta=-40 ta=25 spec 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 vol1[v] ta=25 ta=-40 ta=105 spec iol1[ma] vcc[v] 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5 6 vcc[v] ili[ a] ta=105 ta=25 ta=-40 spec
datasheet datasheet 6/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) figure 6. output leak current ilo(sda) figure 7. current consumption at write operation icc1 (fscl=400khz) figure 9. current consumption at read operation icc2 (fscl=400khz) figure 8. current consumption at write operation icc1 (fscl=400khz) typical performance curves \ continued 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 vcc[v] ilo[ a] spec ta=105 ta=25 ta=-40 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 6 vcc[v] icc1[ma] fscl=400khz data=aah ta=25 ta=105 ta=-40 spec [br24a01a/02/04/08/16-wm] 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 vcc[v] icc2[ma] fscl=400khz data=aah ta=25 ta=-40 ta=105 spec 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 1 2 3 4 5 6 icc1[ma] fscl=400khz data=aah ta=25 ta=105 ta=-40 spec [br24a32/64-wm] vcc[v]
datasheet datasheet 7/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) figure 10. current consumption at write operation icc1 (fscl=100khz) figu r e 11. current consumpt ion at write operation icc1 (fscl=100khz) figure 12. current consumption at read operation icc2 (fscl=100khz) figure 13. standby current isb typical performance curves \ continued vcc[v] vcc[v] 0 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 vcc[v] icc1[ma] fscl=100khz data=aah ta=25 ta=105 ta=-40 spec [br24a01a/02/04/08/16-wm] 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0123 4 56 icc1[ma] ta=25 ta=105 ta=-40 [br24a32/64-wm] spec fscl=100khz data=aah 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 vcc[v] icc2[ma] spec fscl=100khz data=aah ta=-40 ta=105 ta=25 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 6 isb[ a] ta=-40 ta=105 ta=25 spec
datasheet datasheet 8/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) figure 14. scl frequency fscl figure 15. data clo ck "h" time thigh figure 16. data clock "l" time tlow figure 17. start condition hold time thd:sta typical performance curves \ continued 1 10 100 1000 10000 0 1 2 3 4 5 6 vcc[v] fscl[khz] ta=105 ta=25 ta=-40 spec2 spec1 0 1 2 3 4 5 0123 4 56 vcc[v] thigh [ s] spec2 ta=-40 ta=25 ta=105 spec1 0 1 2 3 4 5 0 1 2 3 4 5 6 vcc[v] tlow[ s] spec2 spec1 ta=105 ta=25 ta=-40 0 1 2 3 4 5 0123 4 56 thd:sta[ s] spec2 spec1 ta=105 ta=25 ta=-40 vcc[v]
datasheet datasheet 9/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) figure 18. start condition setup time tsu:sta figure 19. input data hold time thd:dat(high) figure 20. input data hold time thd:dat(low) figure 21. input data setup time tsu:dat(high) typical performance curves \ continued -200 -150 -100 -50 0 50 0123 4 56 vcc[v] thd:dat(high)[ns] spec1, 2 ta=-40 ta=25 ta=105 0 1 2 3 4 5 6 0 1 2 3 4 5 6 vcc[v] tsu:sta[ s] spec2 spec1 ta=-40 ta=25 ta=105 -200 -150 -100 -50 0 50 0 1 2 3 4 5 6 thd:dat(low)[ns] spec1, 2 ta=-40 ta=105 ta=25 vcc[v] -200 -100 0 100 200 300 0123 4 56 vcc[v] tsu:dat(high)[ns] ta=105 ta=25 ta=-40 spec1 spec2
datasheet datasheet 10/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) figure 22. input data setup time tsu:dat(low) figure 23. output data delay time tpd0 figure 24. output data delay time tpd1 figure 25. bus release time before transfer start tbuf typical performance curves \ continued -200 -100 0 100 200 300 0 1 2 3 4 5 6 vcc[v] tsu:dat(low)[ns] ta=-40 ta=105 ta=25 spec1 spec2 0 1 2 3 4 5 0123 4 56 vcc[v] tbuf[ s] spec2 spec1 ta=-40 ta=25 ta=105 0 1 2 3 4 0123 4 56 vcc[v ] tpd0[ s] ta=105 ta=25 ta=-40 spec 2 spec 1 spec 2 spec 1 0 1 2 3 4 0 1 2 3 4 5 6 vcc[v] tpd1[ s] spec1 spec2 spec2 ta=-40 ta=25 ta=105 spec1
datasheet datasheet 11/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) figure 28. noise removal valid time ti(scl l) figure 29. noise removal valid time ti(sda h) figure 26. internal write cycle time twr figure 27. noise removal valid time ti(scl h) typical performance curves \ continued 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 vcc [ v ] ti(scl l)[ s] ta=-40 ta=25 ta=105 spec1 0 1 2 3 4 5 6 0 1 2 3 4 5 6 vcc[v] twr[ms] spec1, 2 ta=25 ta=-40 ta=105 0 0.1 0.2 0.3 0.4 0.5 0.6 0123 4 56 vcc[v] ti(scl h)[ s] spec1, 2 ta=-40 ta=25 ta=105 0 0.1 0.2 0.3 0.4 0.5 0.6 0123 4 56 vcc[v] ti(sda h)[ s] spec1, 2 ta=25 ta=-40 ta=105
datasheet datasheet 12/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) figure 30. noise removal valid time ti(sda l) figure 31. wp setup time tsu:wp figure 32. wp valid time thigh:wp typical performance curves \ continued 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 ti(sda l)[ s] spec1 ta=-40 ta=105 ta=25 vcc[v] -0.6 -0.4 -0.2 0 0123 4 56 vcc[v] tsu:wp[ s] spec1, 2 ta=105 ta=-40 ta=25 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 vcc[v] thigh:wp[ s] spec1, 2 ta=-40 ta=25 ta=105
datasheet datasheet 13/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) i 2 c bus communication i 2 c bus data communication i 2 c bus data communication starts by start condition input, and e nds by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices connected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are ?master? that generates clock and control communicati on start and end, and ?slave? that is controlled by address peculiar to devices. eeprom becomes ?slave?. and the device th at outputs data to bus during data communication is called ?transmitter?, and the dev ice that receives data is called ?receiver?. start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. ? this ic always detects whether sda and scl are in start condition (start bit) or not, therefore, unless this confdition is satisfied, any command is executed. stop condition (stop bit recongnition) ? each command can be ended by sda rising from 'low' to 'high' when stop condition (stop bit), namely, scl is 'high' acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to sh ow whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write comm and, read command, and this ic at data output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data. ? the device (this ic at slave address in put of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda 'low ' during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) 'low'. ? each write operation outputs acknowledge signal (ack si gnal) 'low', at receiving 8bit data (word address and write data). ? each read operation outputs 8bit data (read data), and detects acknowledge signal (ack signal) 'low'. ? when acknowledge signal (ack signal) is detected, a nd stop condition is not s ent from the master ( -com) side, this ic continues data output. when acknowledge signal (ack si gnal) is not detected, this ic stops data transfer, and recognizes stop condition (stop bit), and ends read operation. and this ic gets in status. device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to '1010'. ? next slave addresses (a2 a1 a0 --- device address) are for se lecting devices, and plural ones can be used on a same bus according to the number of device addresses. ? the most insignificant bit (r/w --- read / write) of slave address is used for designating write or read operation, and is as shown below. setting r / w to 0 ------- write (setting 0 to word address setting of random read) setting r / w to 1 ------- read type slave address maximum number of connected buses br24a01a-wm 1 0 1 0 a2 a1 a0 r/w D 8 br24a02-wm 1 0 1 0 a2 a1 a0 r/w D 8 br24a04-wm 1 0 1 0 a2 a1 ps r/w D 4 br24a08-wm 1 0 1 0 a2 p1 p0 r/w D 2 br24a16-wm 1 0 1 0 p2 p1 p0 r/w D 1 br24a32-wm 1 0 1 0 a2 a1 a0 r/w D 8 br24a64-wm 1 0 1 0 a2 a1 a0 r/w D 8 ps, p0 to p2 are page select bits. note) up to 4 units br24a04-wm, up to 2 units of br24a08-wm, and one unit of br24a16-wm can be connected. device address is set by 'h' and 'l' of each pin of a0, a1, and a2. figure 33. data transfer timing 1 1 1 2 1 3 1 4 1 8 1 6 1 5 br24a01a-wm br24a02-wm br24a04-wm br24a08-wm br24a16-wm br24a32-wm br24a64-wm a0 1 7 a1 a2 gnd vcc wp scl sda 89 89 89 s p condition condition ack stop ack data data addres s start r/w ack 1-7 sda scl 1-7 1-7
datasheet datasheet 14/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) write command write cycle ? arbitrary data is written to eeprom. when to write only 1 byte, byte write is normally used, an d when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. the maximum number of write bytes is specified per device of each capacity. up to 32 arbitrary bytes can be written. (in the case of br24a32 / a64-wm) ? data is written to the address designated by word address (n-th address) ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, the following can be written in bulk : up to 8 bytes ( br24a01a-wm, br24a02-wm : up to 16bytes (br24a04-wm, br24a08-wm,br24a16-wm : up to 32bytes (br24a32-wm, br24a64-wm and when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (refer to "internal address increment" in page 15.) ? as for page write cycle of br24a01a-wm and br24a02-wm, after the significant 5 bits (4 significant bits in br24a01a-wm) of word address are designated arbitrarily, and as for page write command of br24a04-wm, br24a08-wm, and br24a16-wm, after page select bit (ps) of sl ave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in br24a01a-wm, and br24a02-wm) is incremented internally, and data up to 16 bytes (up to 8 bytes in br24a01a-wm and br24a02-wm) can be written. ? as for page write cycle of br24a32-wm and br24a64-wm, after the significant 7 bits (in the case of br24a32-wm) of word address, or the significant 8 bits (in the case of br24a64-wm) of word address are designated arbitrarily, by continuing data input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. w r i t e s t a r t r / w a c k s t o p word address(n) dat a (n) sda line a c k a c k data(n+15) a c k slave address 1 0 0 1a0 a1 a2 wa 7 d0 d7 d0 wa 0 note) *1 *2 a1 a2 wa 7 d7 1 1 0 0 w r i t e s t a r t r / w s t o p word address data slave address a0 wa 0 d0 a c k sda line a c k a c k note) *1 figure 34. byte write cycle (br24a01a/02/04/08/16-wm) *1 as for wa7, br24a01a-wm becomes don?t care. a1 a2 1 1 0 0 w r i t e s t a r t r / w s t o p 1st word address data slave address a0 d0 a c k sda line a c k a c k note) wa 12 wa 11 * wa 0 a c k 2nd word address d7 *1 * * *1 as for wa12, br24a32-wm becomes don?t care. figure 35. byte write cycle (br24a32/64-wm) *1 as for wa7, br24a01a-wm becomes don?t care. *2 as for br24a01a/02-wm become (n+7). figure 36. page write cycle (br24a01a/02/04/08/16-wm) figure 37. page write cycle (br24a32/64-wm) *1 as for wa12, br24a32-wm becomes don?t care. w r i t e s t a r t r / w a c k s t o p 1st w ord address(n) sda line a c k a c k data(n+31) a c k slave address 1 0 0 1a0 a1 a2 d0 note) *1 data(n) d0 d7 a c k 2nd w ord address(n) wa 0 wa 12 wa 11 * * * note) 1 0 0 1a0 a1 a2 *1 *2 *3 figure 38. difference of slave address of each *1 in br24a16-wm, a2 becomes p2. *2 in br24a08-wm, br24a16-wm, a1 become p1. *3 in br24a04-wm, a0 becomes ps, and in br24a08-wm and
datasheet datasheet 15/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) notes on write cycle continuous input notes on page write cycle list of numbers of page write number of pages 8byte 16byte 32byte product number br24a01a-wm br24a02-wm br24a04-wm br24a08-wm br24a16-wm br24a32-wm br24a64-wm the above numbers are maximum bytes for respective types. any bytes below these can be written. in the case br24a02-wm, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write. it does not stand 5ms at maximum 8byte=40ms(max.). internal address increment page write mode (in the case of br24a02-wm) for example, when it is started from address 06h, therefore, incremen t is made as below, 06h 07h 00h 01h ---, which please note. *06h ??? 06 in hexadecimal, therefore, 00000110 becomes a binary number. write protect (wp) terminal ? write protect (wp) function when wp terminal is set v cc (h level), data rewrite of all addresses is prohibit ed. when it is set gnd (l level), data rewrite of all address is enabled. be sure to connect this terminal to v cc or gnd, or control it to h leve l or l level. do not use it open. at extremely low voltage at power on / off, by setti ng the wp terminal 'h', mistake write can be prevented. during twr, set the wp terminal al ways to 'l'. if it is set 'h ', write is forcibly terminated. w r i t e s t a r t r / w a c k s t o p word address? data(n) sda line a c k data(n+7) a c k slave address 10 0 1a0 a1 a2 wa 7 d0 d7 d0 *1 a c k note) wa 0 1 1 00 next command twr(maximum : 5ms) command is not accepted for this period. at stop (stop bit), write starts. *2 *3 s t a r t *1 br24a01a-wm becomes don?t care. *2 br24a04-wm, br24a08-w, and br24a16-wm become (n+15). *3 br24a32-wm and br24a64-wm become (n+31). 1 0 0 1a0 a1 a2 *1 *2 *3 figure 40. difference of each type of slave address figure 39. page write cycle *1 in br24a16-wm, a2 becomes p2. *2 in br24a08-wm, br24a16-wm, a1 become p1. *3 in br24a04-wm, a0 becomes ps, and in br24a08-wm and in br24a16-wm, a0 becomes p0. note) wa7 ----- wa4 wa3 wa2 wa1 wa0 0 ----- 0 0 0 0 0 0 ----- 0 0 0 0 1 0 ----- 0 0 0 1 0 0 ----- 0 0 1 1 0 0 ----- 0 0 1 1 1 0 ----- 0 0 0 0 0 --------- --------- --------- 06h significant bit is fixed. no digit up increment
datasheet datasheet 16/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) read command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used generally. current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. in both the read cycles, sequential read cycle is availabl e, and the next address data can be read in succession. ? in random read cycle, data of desig nated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-t h address, i.e., data of t he (n+1)-th address is output. ? when ack signal 'low' after d0 is detected, and stop condition is not sent from master ( -com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where 'h' is input to ack si gnal after d0 and sda signal is started at scl signal 'h' . ? when 'h' is not input to ack signal after d0, sequ ential read gets in, and the next data is output. therefore, read command cycle cannot be ended. when to end read command cycle, be sure input stop condition to input 'h' to ack signal after d0, and to start sda at scl signal 'h'. ? sequential read is ended by stop condition where 'h' is input to ack signal after arbitrary d0 and sda is started at scl signal 'h'. w r i t e s t a r t r / w a c k s t o p word address(n) sda line a c k a c k data(n) a c k slave address 10 0 1 a0 a1 a2 wa 7 a0 d0 slave address 10 0 1a1 a2 s t a r t d7 r / w r e a d wa 0 n ote ) *1 it is necessary to input 'h' to the last ack. figure 41. random read cycle (br24a01a/02/04/08/16-wm) w r i t e s t a r t r / w a c k s t o p 1st word address? sda line a c k a c k data(n) a c k slave address 1 0 0 1 a0 a1 a2 d7 d0 * 2nd word address? a c k s t a r t slave address 1 0 0 1 a2 a1 r / w r e a d a0 wa 0 note) * 1 wa 12 wa 11 ** figure 42. random read cycle (br24a32/64 -wm) *1 as for wa12, br24a32-wm become don?t care. *1 as for wa7, br24a01a-wm become don?t care. s t a r t s t o p sda line a c k data(n) a c k slave address 10 0 1 a0 a1 a2 d0 d7 r / w r e a d note) figure 43. current read cycle it is necessary to input 'h' to the last ack. r e a d s t a r t r / w a c k s t o p data(n) sda line a c k a c k data(n+x) a c k slave address 10 0 1 a0 a1 a2 d0 d7 d0 d7 note figure 44. sequential read cycle (in the case of current read cycle) *1 in br24a16-wm, a2 becomes p2. *2 in br24a08-wm, br24a16-wm, a1 become p1. *3 in br24a04-wm, a0 becomes ps, and in br24a08-wm and br24a16-wm, a0 becomes p0. 1 0 0 1a0 a1 a2 *1 *2 *3 note) figure 45. difference of slave address of each type
datasheet datasheet 17/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) software reset software reset is executed when to avoid malfunction afte r power on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the figur e below. (refer to figure 46(a), figure 46(b), and figure 46(c).) in dummy clock input area, release the sda bus ('h' by pull up). in dummy clock area, ack output and read data '0' (both 'l' level) may be output from eeprom, therefore, if 'h' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. acknowledge polling during internal write execution, all input commands are ignor ed, therefore ack is not sent back. during internal automatic write execution after write cycle input, next command (slave addre ss) is sent, and if the first ack signal sends back 'l', then it means end of write operation, while if it sends back 'h', it means now in writing. by use of acknowledge polling, next command can be executed without waiting for twr = 5ms. when to write continuously, r/w = 0, when to carry out current read cycle after write, slave address r/w = 1 is sent, and if ack signal sends back 'l', then execute word address input and data output and so forth. figure 47. case to continuously write by acknowledge polling 1 2 13 14 scl dummy clock14 start2 figure 46-(a) the case of dummy clock +start+start+ command input start command from start input. 2 1 8 9 dummy clock9 start figure 46-(b) the case of start +9 dummy clocks +start+ command input start normal command normal command normal command normal command start9 sda 1 2 3 8 9 7 figure 46-(c) start9+ command input normal command normal command scl sda scl sda s t a r t first write command a c k h slave address slave address write command during internal write, ack = high is sent back. t wr second write command s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l slave address word address a c k l slave address data after completion of internal write, ack=low is sent back, so input next word address and data in succession. t wr s t a r t s t a r t s t o p a c k h a c k l
datasheet datasheet 18/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to cancel write cycle and so forth, pa y attention to the following wp valid timing. during write cycle execution, in cancel valid area, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in d0 of data(in page write cycle, the first byte data) is cancel invalid area. wp input in this area becomes don't care. set the setup time to rise of d0 taken scl 100ns or more. the area from the rise of scl to take in d0 to the end of intern al automatic write (twr) is cancel valid area. and, when it is set wp='h' during twr, write is ended forcibly, data of address under access is not guaran teed, therefore, writ e it once again. (refer to figure 48 . ) after execution of forced end by wp, standby status gets in, so there is no need to wait for twr (5ms at maximum). command cancel by start condition and stop condition during command input, by continuously inputting start condition and stop condition, command can be cancelled. (refer to figure 49.) however, in ack output area and during data read, sda bus ma y output 'l', and in this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. and when command is cancelled by start, stop condition, during random read cycle, sequential read cycl e, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out curre nt read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. figure 48. wp valid timing figure 49. case of cancel by start, stop condition during slave address input scl sda 1 1 0 0 start condition stop condition wp wp cancels invalid area wp cancels valid area write forced end data is not written. data not guaranteed s t a r t a c k l ? rise of d0 taken clock scl d0 ack enlarged view scl sda enlarged view ack d0 ? rise of sda sda d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 a c k l a c k l a c k l s t o p word address slave address
datasheet datasheet 19/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) i/o peripheral circuit pull up resistance of sda terminal sda is nmos open drain, so requires pull up resistance. as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, operating frequency is limited. the smaller the r pu , the larger the consumpt ion current at operation. maximum value of r pu the maximum value of r pu is determined by the following factors. (1)sda rise time to be determined by the capacitance (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of 'h' to sda bus and rpu should sufficiently secure the input 'h' leve l (vih) of microcontroller and eeprom including recommended noise margin 0.2 v cc . minimum value of r pu the minimum value of r pu is determined by the following factors. (1)when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. (2)v olmax =0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1 v cc . v olmax Q v il -0.1 v cc ex. ) when v cc =3v, vol=0.4v, iol=3ma, microcontroller, eeprom vil=0.3 v cc from (1) therefore, the condition (2) is satisfied. pull up resistance of scl terminal when scl control is made at cmos output port, there is no need, but in the ca se there is timing where scl becomes 'hi-z', add a pull up resistance. as for the pull up resistance, one of several k to several ten k is recommended in consideration of drive performance of output port of microcontroller. a0, a1, a2, wp process process of device address terminals (a0,a1,a2) check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. connect this terminal to pull up or pull down, or v cc or gnd. and, pins (n, c, pin) not used as device addre ss may be set to any of ?h?, 'l', and 'hi-z'. types with n.c.pin br24a16/f/fj -wm a0, a1, a2 br24a08/f/fj-wm a0, a1 br24a04/f/fj -wm a0 process of wp terminal wp terminal is the terminal that prohibits and permits write in hardware manner. in 'h' status, only read is available and write of all address is prohibited. in t he case of 'l', both are available. in the case of use it as an rom, it is recommended to connect it to pull up or v cc . in the case to use both read and write, control wp terminal or connect it to pull down or gnd. r pu R 3 0.4 3 10 -3 R 867 [ ] and v ol = 0.4 [v] v il = 0.3 3 = 0.9 [v] r pu = ex. ) when v cc =3v, i l =10 a, v ih =0.7 v cc , from (2) 0.8 3 - 0.7 3 1010 -6 r pu Q Q 300 [k ] 0.8vcc - v ih i l vcc - i l r pu - 0.2vcc R v ih v c -v ol i ol v cc -v ol r pu Q i ol r pu Q cbus figure 50. i/o circuit diagram r pu a br24axx sda terminal il il microcontroller bus line capacity cbus
datasheet datasheet 20/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) cautions on microcontroller connection rs in i 2 c bus, it is recommended that sda port is of open drain in put/output. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs bet ween the pull up resistance rpu an d the sda terminal of eeprom. this is controls over current that occurs when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sd a terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. maximum value of rs the maximum value of rs is determined by the following relations. (1)sda rise time to be determined by the capacity (cbus) of bus line of rpu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by rpu and rs the moment when eeprom outputs 'l' to sda bus should sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1 v cc . figure 53. i/o circuit diagram minimum value of rs the minimum value of rs is determined by over current at bus collisio n. when over current flows, noises in power source line, and instantaneous power failure of power source may occu r. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable current in consideration of impedance of power source line in set and so forth. set the over current to eeprom 10ma or below. figure 54. i/o circuit diagram microcontroller eeprom 'l' output r s r pu 'h' output over current v cc r s v cc i R 300 ?? example when v cc =3v, i=10ma r s R 3 1010 -3 Q i r s R example when v cc =3v, v il =0.3v cc, v ol =0.4v, r pu =20k , Q v il v ol 0.1v cc 1.1v cc v il 1.13 0.33 0.33 0.4 0.13 r s 1.67k? r pu +r s (v cc v ol )r s +v ol +0.1v cc Qv il r s Q from(2), r pu Q 2010 3 r pu microcontroller r s eeprom figure 51. i/o circuit diagram figure 52. input / output collision timing over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. ack 'l' output of eeprom 'h' output of microcontroller scl sda r pu microcontroller r s eeprom i ol a bus line capacity cbus v ol v cc v il
datasheet datasheet 21/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) i 2 c bus input / output circuit input (a0,a2,scl) input / output (sda) input (a1, wp) notes on power on at power on, in ic internal circuit and set, v cc rises through unstable low voltage area, and ic inside is not completely reset, and malfunction may occur. to prevent this, functions of por ci rcuit and lvcc circuit are equipped. to assure the operation, observe the following conditions at power on. 1. set sda = 'h' and scl ='l' or 'h' 2. start power source so as to satisfy the recommended conditions of t r , t off , and vbot for operating por circuit. recommended conditions of t r , t off ,vbot t r t off vbot 10ms or below 10ms or longer 0.3v or below 100ms or below 10ms or longer 0.2v or below figure 55. input pin circuit diagram figure 56. input / output pin circuit diagram figure 57. input pin circuit diagram t off t r vbot 0 v cc figure 58. rise waveform diagram
datasheet datasheet 22/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above condition 1 cannot be observed. when sda becomes 'l' at power on. control scl and sda as shown below, to make scl and sda, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(page 17). c) in the case when the above cond itions 1 and 2 cannot be observed. carry out a), and then carry out b). low voltage malfunction prevention function lvcc circuit prevents data rewrite operation at low power, and pr events wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. v cc noise countermeasures bypass capacitor when noise or surge gets in the power source line, malfun ction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1 f) between ic v cc and gnd. at that mom ent, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board v cc and gnd. note of use (1) described numeric values and data are design repres entative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your de cision with sufficient margin in consideration of static characterist ics and transition characteristics and fluc tuations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage and operation temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperatur e exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physical sa fety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4)gnd electric potential set the voltage of gnd terminal lowest at any operating condition. make sure that each terminal voltage is lower than that of gnd terminal. (5)terminal design in consideration of permissible loss in actual use cond ition, carry out heat design with sufficient margin. (6)terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay sufficient attention to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shortcircuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause ma lfunction, therefore, eval uate design sufficiently. t low t su:dat t dh a fter vcc becomes stable scl v cc sda after vcc becomes stable t su:dat figure 59. when scl= 'h' and sda= 'l' figure 60. when scl='l' and sda='l'
datasheet datasheet 23/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) ordering information product code description b r 2 4 a x x x x x - wm x x bus type 24: i 2 c operating temperature -40 to +105 capacity 01a=1k 08=8k 64=64k 02=2k 16=16k 04=4k 32=32k package f : sop8 fj : sop-j8 fvm : msop8 double cell packaging and forming specification e2 : embossed tape and reel (sop8,sop-j8) tr : embossed tape and reel (msop8) lineup package capacity type quantity sop8 reel of 2500 1k sop-j8 reel of 2500 sop8 reel of 2500 sop-j8 reel of 2500 2k msop8 reel of 3000 sop8 reel of 2500 4k sop-j8 reel of 2500 sop8 reel of 2500 8k sop-j8 reel of 2500 sop8 reel of 2500 16k sop-j8 reel of 2500 32k sop8 reel of 2500 64k sop8 reel of 2500 status of this document the japanese version of this document is fo rmal specification. a customer may use this translation version only for a reference to help reading the formal version. if there are any differences in translation version of this document formal version takes priority.
datasheet datasheet 24/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) physical dimension tape and reel information ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin (unit : mm) sop8 0.90.15 0.3min 4 + 6 ? 4 0.17 +0.1 - 0.05 0.595 6 43 8 2 5 1 7 5.00.2 6.20.3 4.40.2 (max 5.35 include burr) 1.27 0.11 0.420.1 1.50.1 s 0.1 s
datasheet datasheet 25/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) physical dimension tape and reel information \ continued ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin (unit : mm) sop-j8 4 + 6 ?4 0.20.1 0.45min 234 5678 1 4.90.2 0.545 3.90.2 6.00.3 (max 5.25 include burr) 0.420.1 1.27 0.175 1.3750.1 0.1 s s
datasheet datasheet 26/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) physical dimension tape and reel information \ continued (unit : mm) msop8 0.08 s s 4.00.2 8 3 2.80.1 1 6 2.90.1 0.475 4 57 (max 3.25 include burr) 2 1pin mark 0.9max 0.750.05 0.65 0.080.05 0.22 +0.05 ?0.04 0.60.2 0.290.15 0.145 +0.05 ?0.03 4 + 6 ?4 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs tr () 1pin
datasheet datasheet 27/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) marking diagrams marking information capacity product name marking package type sop8 1k a01a sop-j8 sop8 sop-j8 2k a02 msop8 sop8 4k a04 sop-j8 sop8 8k a08 sop-j8 sop8 16k a16 sop-j8 32k a32 sop8 64k a64 sop8 sop8(top view) part number marking lot numbe r 1pin mark sop-j8(top view) part number marking lot numbe r 1pin mark msop8(top view) part number marking lot number 1pin mark
datasheet datasheet 28/28 tsz02201-0r1r0g100140-1-2 ? 2012 rohm co., ltd. all rights reserved. 31.aug.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 br24axxx-wm (1k 2k 4k 8k 16k 32k 64k) revision history date revision changes 31.aug.2012 001 new release
datasheet datasheet notice - rev.004 ? 2013 rohm co., ltd. all rights reserved. notice general precaution 1. before you use our products, you are requested to care fully read this document and fully understand its contents. rohm shall not be in any way responsible or liable for fa ilure, malfunction or accident arising from the use of any rohm?s products against warning, caution or note contained in this document. 2. all information contained in this document is current as of the issuing date and subjec t to change without any prior notice. before purchasing or using rohm?s products, please confirm the la test information with a rohm sales representative. precaution on using rohm products 1. if you intend to use our products in devices requirin g extremely high reliability (such as medical equipment, aircraft/spacecraft, nuclear power controllers, etc.) and whos e malfunction or failure may cause loss of human life, bodily injury or serious damage to property (?specific applications?), please consult with the rohm sales representative in advance. unless otherwise agreed in writ ing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses in curred by you or third parties arising from the use of any rohm?s products for specific applications. 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are not designed under any special or extr aordinary environments or conditi ons, as exemplified below. accordingly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any rohm?s products under an y special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8. confirm that operation temperat ure is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document.
datasheet datasheet notice - rev.004 ? 2013 rohm co., ltd. all rights reserved. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used; if flow soldering met hod is preferred, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own indepen dent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohm?s internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under cont rolled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or ot her damages arising from use of such information or data.: 2. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the information contained in this document.
datasheet datasheet notice - rev.004 ? 2013 rohm co., ltd. all rights reserved. other precaution 1. the information contained in this document is provi ded on an ?as is? basis and rohm does not warrant that all information contained in this document is accurate and/or error-free. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or concerning such information. 2. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 3. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 4. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 5. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties.

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